//GPT's work again

`timescale 1ns/1ps

module Rotate_Right_tb;

    // Inputs
    reg [31:0] ror_src1;
    reg [31:0] ror_src2;

    // Outputs
    wire [31:0] ror_result;

    // Instantiate the Unit Under Test (UUT)
    Rotate_Right uut (
        .ror_src1(ror_src1),
        .ror_src2(ror_src2),
        .ror_result(ror_result)
    );

    // Testbench logic
    initial begin
        // Initialize Inputs
        ror_src1 = 0;
        ror_src2 = 0;

        // Wait for global reset to finish
        #100;

        // Test case 1: Rotate right by 1 bit
        ror_src1 = 1;
        ror_src2 = 32'h00000001;
        #10;
        $display("Test case 1: ror_src1 = %h, ror_src2 = %h, ror_result = %h", ror_src1, ror_src2, ror_result);

        // Test case 2: Rotate right by 2 bits
        ror_src1 = 2;
        ror_src2 = 32'h00000001;
        #10;
        $display("Test case 2: ror_src1 = %h, ror_src2 = %h, ror_result = %h", ror_src1, ror_src2, ror_result);

        // Test case 3: Rotate right by 3 bits
        ror_src1 = 3;
        ror_src2 = 32'h00000001;
        #10;
        $display("Test case 3: ror_src1 = %h, ror_src2 = %h, ror_result = %h", ror_src1, ror_src2, ror_result);

        // Test case 4: Rotate right by 4 bits
        ror_src1 = 4;
        ror_src2 = 32'h00000001;
        #10;
        $display("Test case 4: ror_src1 = %h, ror_src2 = %h, ror_result = %h", ror_src1, ror_src2, ror_result);

        // Test case 5: Rotate right by 16 bits
        ror_src1 = 16;
        ror_src2 = 32'h00000001;
        #10;
        $display("Test case 5: ror_src1 = %h, ror_src2 = %h, ror_result = %h", ror_src1, ror_src2, ror_result);

        // Test case 6: Rotate right by 31 bits
        ror_src1 = 31;
        ror_src2 = 32'h00000001;
        #10;
        $display("Test case 6: ror_src1 = %h, ror_src2 = %h, ror_result = %h", ror_src1, ror_src2, ror_result);

        // Test case 7: Rotate right by 32 bits (should be the same as no rotation)
        ror_src1 = 32;
        ror_src2 = 32'h00000001;
        #10;
        $display("Test case 7: ror_src1 = %h, ror_src2 = %h, ror_result = %h", ror_src1, ror_src2, ror_result);

        // Test case 8: Rotate right by 5 bits with a different input pattern
        ror_src1 = 5;
        ror_src2 = 32'hF0F0F0F0;
        #10;
        $display("Test case 8: ror_src1 = %h, ror_src2 = %h, ror_result = %h", ror_src1, ror_src2, ror_result);

        // Test case 9: Rotate right by 8 bits with a different input pattern
        ror_src1 = 8;
        ror_src2 = 32'h12345678;
        #10;
        $display("Test case 9: ror_src1 = %h, ror_src2 = %h, ror_result = %h", ror_src1, ror_src2, ror_result);

        // Test case 10: Rotate right by 0 bits (no rotation)
        ror_src1 = 0;
        ror_src2 = 32'h12345678;
        #10;
        $display("Test case 10: ror_src1 = %h, ror_src2 = %h, ror_result = %h", ror_src1, ror_src2, ror_result);

        // End simulation
        $stop;
    end

endmodule